1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a dynamic random access memory (DRAM) having a trench capacitor.
2. Description of the Related Art
In general, in a memory having a trench capacitor, the capacitor has a MOS structure wherein the capacitor is constructed in the form of a trench. This structure of the trench capacitor effectively increases the area of the capacitor, and accordingly, it is possible to provide a small size trench capacitor having a large storage capacitance.
In the prior art memory having a trench capacitor, sometimes the concentration of impurities in the semiconductor substrate is usually low, for example, the substrate impurity concentration 2.times.10.sup.15 cm.sup.-3. In a prior art device including a semiconductor substrate having a low impurity concentration, a punch-through phenomena can occur between the trench capacitor of the memory cell in question and the trench capacitor of the adjacent memory cell, due to an extension of the depletion layer formed in the substrate. This punch-through phenomena is undesirable, since it causes an electrical coupling between adjacent trench capacitors, and accordingly, the stored data is sometimes lost and the memory system becomes less reliable.
In the prior art memory having a trench capacitor, sometimes the so-called Hi-C capacitor structure can be adopted to make the cell plate voltage half-way between Vcc and Vss. In a prior art device having a so-called Hi-C capacitor structure, onset of diffused layer around the trench to form the storage electrode makes the distance between adjacent capacitors still less. This structure leads to the increase of possibility of punch-through between cells. This situation is also undesirable.
Also, in the prior art memory having a trench capacitor, the depletion layer widely expands from the storage electrode in the substrate since the minority carriers produced in the substrate by any means, such as by incidence of an alpha-particle, are quickly captured in the depletion layer to the storage electrode, the possibility of soft errors due to alpha ray irradiation is increased. An increase in the possible occurrence of soft errors is also undesirable.
Further, in the prior art memory having a trench capacitor with inversion layer type electrode, the maximum voltage written into the cell is limited by the cell-plate voltage and lowered by the threshold voltage loss, of forming inversion layer electrons. For example, the maximum available write voltage is reduced to about 1 volt lower than the power source voltage. This reduction of the write voltage from the power source voltage is also undesirable.